參數資料
型號: UPD178006A
廠商: NEC Corp.
英文描述: DDR2, 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer
中文描述: 8位單晶片微控制器
文件頁數: 10/56頁
文件大?。?/td> 314K
代理商: UPD178006A
10
μ
PD178004A, 178006A, 178016A, 178018A
3.2 PINS OTHER THAN PORT PINS
Pin Name
I/O
Function
After Reset
Alternate Function
INTP0 to
INTP6
Input
External maskable interrupt inputs with specifiable valid edges (rising
edge, falling edge, both rising and falling edges).
Input
P00 to P06
SI0
Input
Serial interface serial data input
Input
P25/SB0/SDA0
SI1
P20
SO0
Output
Serial interface serial data output
Input
P26/SB1/SDA1
SO1
P21
SB0
I/O
Serial interface serial data input/output
Input
P25/SI0/SDA0
SB1
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
I/O
Serial interface serial clock input/output
Input
P27/SCL
SCK1
P22
SCL
P27/SCK0
STB
Output
Serial interface automatic transmit/receive strobe output
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input
Input
P24
TI1
Input
External count clock input to 8-bit timer (TM1)
Input
P33
TI2
External count clock input to 8-bit timer (TM2)
P34
BEEP
Output
Buzzer output
Input
P36
ANI0 to ANI5
Input
A/D converter analog input
Input
P10 to P15
PWM0 to PWM2
Output
PWM output
P132 to P134
EO0, EO1
Output
Error out output from charge pump of the PLL frequency synthesizer
VCOL
Input
Inputs PLL local band frequency (In HF, MF mode)
VCOH
Input
Inputs PLL local band frequency (In VHF mode)
AMIFC
Input
Inputs AM intermediate frequency counter
FMIFC
Input
Inputs FM intermediate frequency counter
RESET
Input
System reset input
X1
Input
System clock oscillation resonator connection
X2
REGOSC
Oscillation regulator. Connected to GND via a 0.1-
μ
F capacitor.
REGCPU
CPU power supply regulator. Connected to GND via a 0.1-
μ
F capacitor.
V
DD
Positive power supply
GND
Ground
V
DD
PORT
Positive power supply for port block
GNDPORT
Ground for port block
V
DD
PLL
Note
Positive power supply for PLL
GNDPLL
Note
Ground for PLL
IC
Internally connected. Connected to GND or GNDPORT.
Note
Connect a capacitor of approximately 1 000 pF between the V
DD
PLL pin and GNDPLL pin.
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