參數(shù)資料
型號: UPD178006A
廠商: NEC Corp.
英文描述: DDR2, 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer
中文描述: 8位單晶片微控制器
文件頁數(shù): 23/56頁
文件大小: 314K
代理商: UPD178006A
23
μ
PD178004A, 178006A, 178016A, 178018A
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
Interrupt functions include three types and 17 sources, as shown below.
Non-maskable:
1
Maskable
: 15
Software
:
1
Table 6-1. Interrupt Source List
Non-
maskable
0006H
0008H
000AH
000CH
000EH
0010H
0012H
Trigger
Internal/
External
External
Internal
0004H
0014H
Internal
Vector Table
Address
Interrupt Source
(B)
Basic
Configuration
Type
Note 2
(B)
(A)
(C)
(D)
Maskable
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
1
2
3
4
5
6
7
Note 1
Default
Priority
Name
INTCSI0
8
INTWDT
INTWDT
0
Interrupt
Type
End of serial interface channel 0 transfer
Pin input edge detection
Watchdog timer overflow
(interval timer mode selected)
Watchdog timer overflow
(watchdog timer mode 1 selected)
0016H
9
INTCSI1
End of serial interface channel 1 transfer
0018H
10
INTTMC
Generation of match signal of basic timer
001AH
11
INTPWM
Generation of match signal of 8-bit timer
INTTM1
Generation of match signal of 8-bit timer/
event counter 1
12
001CH
INTTM2
Generation of match signal of 8-bit timer/
event counter 2
001EH
13
14
INTAD
End of conversion by A/D converter
0020H
BRK
BRK instruction execution
003EH
Software
(E)
Internal
Notes
1.
The default priority is a priority order when two or more maskable interrupts are generated
simultaneously. 0 is the highest order and 14, the lowest.
2.
Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
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