參數(shù)資料
型號： UPD44165082F5-E50-EQ1
廠商： NEC Corp.
英文描述： 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
中文描述： 1800萬位推出QDRII SRAM的2字爆發(fā)運(yùn)作
文件頁數(shù)： 10/32頁
文件大小： 385K
代理商： UPD44165082F5-E50-EQ1
10
Data Sheet M15824EJ7V
1
DS
μ
PD44165082, 44165182, 44165362
Bus Cycle State Diagram
READ DOUBLE
WRITE DOUBLE
AT /K
Power UP
Always
Supply voltage
provided
LOAD NEW
READ ADDRESS
READ PORT NOP
R_Init = 0
WRITE PORT NOP
LOAD NEW
WRITE ADDRESS
AT /K
Always
/W = L
Supply voltage
provided
/W = L
/W = H
/W = H
/R = L
/R = L
/R = H
/R = H
Remarks 1.
The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2.
Read and write state machines can be active simultaneously.
3.
State machine control timing sequence is controlled by K.
相關(guān)PDF資料
PDF描述
UPD44165082 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44165182F5-E60-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
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UPD44165362F5-E60-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
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