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參數(shù)資料
| 型號： | UPD44165362F5-E60-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬位推出QDRII SRAM的2字爆發(fā)運作 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 385K |
| 代理商： | UPD44165362F5-E60-EQ1 |
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MOS INTEGRATED CIRCUIT
μ
PD
44165082, 44165182, 44165362
18M-BIT QDR
TM
II SRAM
2-WORD BURST OPERATION
Document No. M15824EJ7V
1
DS00 (7th edition)
Date Published
Jul
y
2004 NS CP(K)
Printed in Japan
DATA SHEET
2001
Description
The
μ
PD44165082 is a 2,097,152-word by 8-bit, the
μ
PD44165182 is a 1,048,576-word by 18-bit and the
μ
PD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
μ
PD44165082,
μ
PD44165182 and
μ
PD44165362 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Two-tick burst for low DDR transaction size
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
μ
s restart
User programmable impedance output
Fast clock cycle time : 5.0 ns (200 MHz), 6.0 ns (167 MHz), 7.5 ns (133 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44165082F5-E75-EQ1 | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| UPD44165182F5-E50-EQ1 | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| UPD44165362F5-E50-EQ1 | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| UPD44321361GF-A75 | 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION |
| UPD44321181 | 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44321182GF-A50(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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