參數(shù)資料
型號(hào)： UPD44165082F5-E60-EQ1
廠商： NEC Corp.
英文描述： 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
中文描述： 1800萬(wàn)位推出QDRII SRAM的2字爆發(fā)運(yùn)作
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 385K
代理商： UPD44165082F5-E60-EQ1
8
Data Sheet M15824EJ7V
1
DS
μ
PD44165082, 44165182, 44165362
Truth Table
Operation
CLK
/R
/W
D or Q
WRITE cycle
L
→
H
X
L
Data in
Load address, input write data on
Input data
D
A
(A+0)
D
A
(A+1)
consecutive K and /K rising edge
Input clock
K( t )
↑
/K( t )
↑
READ cycle
L
→
H
L
X
Data out
Load address, output data on
Output data
Q
A
(A+0)
Q
A
(A+1)
consecutive C and /C rising edge
Output clock
/C(t+1)
↑
C(t+2)
↑
NOP (No operation)
L
→
H
H
H
D=X or Q=High-Z
STANDBY(Clock stopped)
Stopped
X
X
Previous state
Remarks 1.
H : High level, L : Low level,
×
: don’t care,
↑
: rising edge.
2.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.
3.
All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4.
This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5.
Refer to state diagram and timing diagrams for clarification.
6.
It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
相關(guān)PDF資料
PDF描述
UPD44165082F5-E50-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44165082 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44165182F5-E60-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44165182F5-E75-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44165362F5-E60-EQ1 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
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