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參數(shù)資料
| 型號： | UPD44165082F5-E75-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬位推出QDRII SRAM的2字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 385K |
| 代理商： | UPD44165082F5-E75-EQ1 |
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16
Data Sheet M15824EJ7V
1
DS
μ
PD44165082, 44165182, 44165362
Read and Write Timing
K
Address
Data in
/K
2
4
6
8
10
1
3
5
7
9
TKH/KH
T/KHKH
C
/C
TKHCH
NOP
READ
READ
READ
WRITE
WRITE
WRITE
TKHKL
TKLKH
Q00
Q20
Data out
Q01
Q21
Q41
Q40
/R
/W
A1
A3
A2
A4
A6
A5
A0
D11
D31
D30
D50
D61
D51
D10
D60
TKHKL
TKLKH
TKH/KH
T/KHKH
TKHKH
TCHQX1
TCHQV
TCHQX
TCHQX
TCHQZ
TDVKH
TKHDX
TDVKH
TKHDX
TKHKH
TIVKH
TKHIX
TAVKH
TKHAX
TAVKH
TKHAX
NOP
WRITE
CQ
/CQ
TCQHQV
TCHQV
TCHCQV
TCHCQX
TCHCQV
TKHCH
TCHCQX
Remarks 1.
Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2.
Outputs are disable (high impedance) one clock cycle after a NOP.
3.
In this example, if address A0=A1, data Q00=D10, Q01=D11.
Write data is forwarded immediately as read results.
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| UPD44165182F5-E50-EQ1 | 18M-BIT QDRII SRAM 2-WORD BURST OPERATION |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44165362BF5-E40-EQ3 | 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays |
| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
| UPD44321182GF-A50(A) | 制造商:Renesas Electronics Corporation 功能描述: |
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