- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379496 > UPD44324082 (NEC Corp.) 36M-BIT DDRII SRAM 2-WORD BURST OPERATION PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD44324082 |
| 廠商： | NEC Corp. |
| 元件分類： | DRAM |
| 英文描述： | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位SRAM的2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 17/32頁(yè) |
| 文件大?。?/td> | 349K |
| 代理商： | UPD44324082 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
17
Preliminary Data Sheet
M16780EJ2V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Notes 1.
The device will operate at clock frequencies slower than TKHKH(MAX.).
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once V
DD
and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
±
0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5.
This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1.
This parameter is sampled.
2.
Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3.
Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4.
If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5.
V
DD
Q is 1.5 V DC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44324092F5-E50-EQ2 | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324182F5-E50-EQ2 | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324084F5-E33-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
| UPD44324084F5-E40-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
| UPD44324184F5-E40-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44324182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:RENUPD44324182BF5-E40-FQ1-A 36M-BIT(2M-W |
| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。