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參數(shù)資料
| 型號(hào)： | UPD44325084F5-E40-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大小： | 377K |
| 代理商： | UPD44325084F5-E40-EQ2 |
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17
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
Read and Write Cycle
Parameter
Symbol
-E33
-E40
-E50
Unit
Note
(300 MHz)
(250 MHz)
(200 MHz)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time (K, /K, C, /C) TKHKH
Clock phase jitter (K, /K, C, /C)
Clock HIGH time (K, /K, C, /C)
Clock LOW time (K, /K, C, /C)
Clock to /clock (K
→
/K., C
→
/C.)
Clock to /clock (/K
→
K., /C
→
C.)
Clock to data clock 250 to 300 MHz
(K
→
C., /K
→
/C.)
200 to 250 MHz
167 to 200 MHz
133 to 167 MHz
DLL lock time (K, C)
K static to DLL reset
3.3
8.4
4.0
8.4
5.0
8.4
ns
ns
ns
ns
ns
ns
ns
1
2
3
TKC var
TKHKL
TKLKH
TKH /KH
T /KHKH
TKHCH
TKC lock
TKC reset
–
0.2
–
0.2
–
0.2
1.32
–
1.6
–
2.0
–
1.32
–
1.6
–
2.0
–
1.49
–
1.8
–
2.2
–
1.49
–
1.8
–
2.2
–
0
1.45
–
–
–
–
0
1.8
0
1.8
–
–
0
2.3
0
2.3
0
2.3
0
2.8
0
2.8
0
2.8
< 133 MHz
0
3.55
0
3.55
0
3.55
1,024
–
1,024
–
1,024
–
Cycle
ns
30
–
30
–
30
–
Output Times
C, /C HIGH to output valid
C, /C HIGH to output hold
C, /C HIGH to echo clock valid
C, /C HIGH to echo clock hold
CQ, /CQ HIGH to output valid
CQ, /CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
–
0.45
–
0.45
–
0.45
ns
ns
ns
ns
ns
ns
ns
ns
– 0.45
–
– 0.45
–
– 0.45
–
–
0.45
–
0.45
–
0.45
– 0.45
–
– 0.45
–
– 0.45
–
–
0.27
–
0.3
–
0.35
4
4
– 0.27
–
– 0.3
–
– 0.35
–
–
0.45
–
0.45
–
0.45
– 0.45
–
– 0.45
–
– 0.45
–
Setup Times
Address valid to K rising edge
Control inputs (/R, /W) valid to K rising
edge
Data inputs and write data select
inputs (/BWx, /NWx) valid to K, /K
rising edge
TAVKH
TIVKH
TDVKH
0.4
–
0.5
–
0.6
–
ns
ns
ns
5
5
5
0.4
–
0.5
–
0.6
–
0.3
–
0.35
–
0.4
–
Hold Times
K rising edge to address hold
K rising edge to control inputs (/R, /W)
hold
K, /K rising edge to data inputs and
write data select inputs (/BWx, /NWx)
hold
TKHAX
TKHIX
TKHDX
0.4
–
0.5
–
0.6
–
ns
ns
ns
5
5
5
0.4
–
0.5
–
0.6
–
0.3
–
0.35
–
0.4
–
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| UPD44325184F5-E40-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
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| UPD44325094F5-E40-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| UPD44325094F5-E50-EQ2 | 36M-BIT QDRII SRAM 4-WORD BURST OPERATION |
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|---|---|
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
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