參數(shù)資料
型號(hào): UPD44325084F5-E40-EQ2
廠商: NEC Corp.
英文描述: 36M-BIT QDRII SRAM 4-WORD BURST OPERATION
中文描述: 36M條位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作
文件頁數(shù): 19/36頁
文件大小: 377K
代理商: UPD44325084F5-E40-EQ2
19
Preliminary Data Sheet
M16784EJ1V0DS
μ
PD44325084, 44325094, 44325184, 44325364
Read and Write Timing
K
Address
Data in
/K
2
4
6
1
3
5
7
TKH/KH
T/KHKH
C
/C
TKHCH
NOP
READ
READ
TKHKL
TKLKH
Q00
Q02
Data out
Q01
Q03
/R
/W
TKHKL
TKLKH
TCHQX1
TCHQX
TCHQZ
D10
D12
D11
D13
TDVKH
TKHDX
TDVKH
TKHDX
TKHKH
TIVKH
TKHIX
TAVKH
TKHAX
CQ
/CQ
TCQHQV
TCHQV
TCHCQX
TCHCQV
TCHCQX
TCHCQV
WRITE
NOP
Qx3
TCHQX
TCHQV
WRITE
TIVKH
TKHIX
A0
A1
A2
A3
D30
D32
D31
D33
Q20
Q22
Q21
Q23
Qx2
TKH/KH
T/KHKH
TKHCH
TKHKH
Remarks 1.
Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2.
Outputs are disable (high impedance) one clock cycle after a NOP.
3.
In this example, if address A0=A1, data Q00=D10, Q01=D11.
Write data is forwarded immediately as read results.
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UPD44325184F5-E40-EQ2 36M-BIT QDRII SRAM 4-WORD BURST OPERATION
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