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參數(shù)資料
| 型號： | UPD4482162 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
| 中文描述： | 800萬位CMOS同步快速靜態(tài)存儲器流水線操作單周期取消選擇 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 445K |
| 代理商： | UPD4482162 |
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14
Data Sheet M14522EJ3V0DS
μ
PD4482162, 4482182, 4482322, 4482362
Read and Write Cycle
(2.5 V LVTTL Interface)
Parameter
Symbol
-A44, -A50, -A60, -C60
Unit
Note
-A44Y, -A50Y, -A60Y, -C60Y
(167 MHz)
Standard
Alias
MIN.
MAX.
Cycle time
TKHKH
TCYC
6.0
–
ns
Clock access time
TKHQV
TCD
–
3.5
ns
Output enable access time
TGLQV
TOE
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
0
–
ns
Clock high to output change
TKHQX2
TDC2
1.5
–
ns
Output enable to output active
TGLQX
TOLZ
0
–
ns
Output disable to output High-Z
TGHQZ
TOHZ
0
3.5
ns
Clock high to output High-Z
TKHQZ
TCZ
1.5
3.5
ns
Clock high pulse width
TKHKL
TCH
2.0
–
ns
Clock low pulse width
TKLKH
TCL
2.0
–
ns
Setup times
Address
TAVKH
TAS
1.5
–
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance
TADVVKH
–
Chip enable
TEVKH
–
Hold times
Address
TKHAX
TAH
0.5
–
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance
TKHADVX
–
Chip enable
TKHEX
–
Power down entry time
TZZE
TZZE
–
12.0
ns
Power down recovery time
TZZR
TZZR
–
12.0
ns
相關(guān)PDF資料 |
PDF描述 |
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| UPD4482182GF-A50Y | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
| UPD4482182GF-C60 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
| UPD4482182GF-C60Y | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
| UPD4482162GF-A60 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
| UPD4482162GF-A60Y | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT |
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