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參數(shù)資料
| 型號： | UPD4482363GF-A60Y |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| 中文描述： | 800萬位CMOS同步快速靜態(tài)存儲器流水線操作雙循環(huán)取消選擇 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 300K |
| 代理商： | UPD4482363GF-A60Y |
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8
Data Sheet M14904EJ3V0DS
μ
PD4482163, 4482183, 4482323, 4482363
[
μ
PD4482323,
μ
PD4482363]
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Byte 3
Write Register
Byte 3
Write Driver
8/9
Byte 4
Write Register
Byte 4
Write Driver
32/36
8/9
Enable
Register
Row and Column
Decoders
Memory cell array
1,024 rows
256
×
32 columns
(8,388,608 bits)
256
×
36 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
32/36
16
18
A0, A1
A1
’
A0
’
4
32/36
A0 to A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O32
I/OP1 to I/OP4
ZZ
Power Down Control
18
[
μ
PD4482323,
μ
PD4482363]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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