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參數(shù)資料
| 型號： | UPD4483362GF-A75 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 中文描述： | 800萬位CMOS同步快速靜態(tài)內(nèi)存256K - Word的36位HSTL接口/寄存器間/晚寫 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 94K |
| 代理商： | UPD4483362GF-A75 |
9
μ
PD4483362
Preliminary Data Sheet M14440EJ1V0DS
Single Differential Clock, Registered Input / Registered Output Mode
Parameter
Symbol
–
A75 (133 MHz)
Unit
Notes
MIN.
MAX.
Clock cycle time
t
KHKH
7.5
–
ns
Clock phase time
t
KHKL
/
2.0
–
ns
t
KLKH
Setup times
Address
t
AVKH
1.5
–
ns
Write data
t
DVKH
Write enable
t
WVKH
Chip select
t
SVKH
Hold times
Address
t
KHAX
0.5
–
ns
Write data
t
KHDX
Write enable
t
KHWX
Chip select
t
KHSX
Clock access time
t
KHQV
–
3.8
ns
1
K high to Q change
t
KHQX
1.5
–
ns
2
/G low to Q valid
t
GLQV
–
3.8
ns
1
/G low to Q change
t
GLQX
0
–
ns
2
/G high to Q Hi-Z
t
GHQZ
0
3.8
ns
2
K high to Q Hi-Z (/SW)
t
KHQZ
1.5
3.8
ns
2
K high to Q Hi-Z (/SS)
t
KHQZ2
1.5
3.8
ns
2
K high to Q Lo-Z
t
KHQX2
1.5
–
ns
2
Sleep Mode Recovery
t
ZZR
–
7.5
ns
Sleep Mode Enable
t
ZZE
–
7.5
ns
Notes 1.
See figure. (V
TT
= 0.75 V)
DQ (Output)
Z
O
= 50
20 pF
50
V
TT
2.
See figure. (V
TT
= 0.75 V)
DQ (Output)
5 pF
50
V
TT
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