參數(shù)資料
型號(hào): UPD45128163G5-A10I-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 6/86頁
文件大?。?/td> 785K
代理商: UPD45128163G5-A10I-9JF
Data Sheet E0346N10 (Ver. 1.0)
6
μ
PD45128163-I
CONTENTS
1.
2.
3.
4.
Input / Output Pin Function ............................................................................................................. 8
Commands ........................................................................................................................................ 9
Simplified State Diagram ............................................................................................................... 12
Truth Table ...................................................................................................................................... 13
4.1 Command Truth Table............................................................................................................................ 13
4.2 DQM Truth Table..................................................................................................................................... 13
4.3 CKE Truth Table...................................................................................................................................... 13
4.4 Operative Command Table .................................................................................................................... 14
4.5 Command Truth Table for CKE ............................................................................................................. 17
5.
6.
7.
Initialization ..................................................................................................................................... 18
Programming the Mode Register .................................................................................................. 19
Mode Register ................................................................................................................................. 20
7.1 Burst Length and Sequence ................................................................................................................. 21
8.
9.
10. Auto Precharge ............................................................................................................................... 24
10.1
Read with Auto Precharge .................................................................................................................. 24
10.2
Write with Auto Precharge ................................................................................................................. 25
11. Read / Write Command Interval .................................................................................................... 26
11.1
Read to Read Command Interval ....................................................................................................... 26
11.2
Write to Write Command Interval ....................................................................................................... 26
11.3
Write to Read Command Interval ....................................................................................................... 27
11.4
Read to Write Command Interval ....................................................................................................... 28
12. Burst Termination ........................................................................................................................... 29
12.1
Burst Stop Command ......................................................................................................................... 29
12.2
Precharge Termination ....................................................................................................................... 30
Address Bits of Bank-Select and Precharge ................................................................................ 24
Precharge ........................................................................................................................................ 23
12.2.1 Precharge Termination in READ Cycle ................................................................................... 30
12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 31
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