參數(shù)資料
型號(hào): UPD45128163G5-A10LI-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 36/86頁
文件大?。?/td> 785K
代理商: UPD45128163G5-A10LI-9JF
Data Sheet E0346N10 (Ver. 1.0)
36
μ
PD45128163-I
Asynchronous Characteristics
Parameter
Symbol
-A75
-A80
-A10
Unit
Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
ACT to REF/ACT command period (operation)
t
RC
67.5
70
70
ns
REF to REF/ACT command period (refresh)
t
RC1
67.5
70
70
ns
ACT to PRE command period
t
RAS
45
120,000
48
120,000
50
120,000
ns
PRE to ACT command period
t
RP
20
20
20
ns
Delay time ACT to READ/WRITE command
t
RCD
20
20
20
ns
ACT (one) to ACT (another) command period
t
RRD
15
16
20
ns
Data-in to PRE command period
t
DPL
15
15
15
ns
Data-in to ACT (REF)
command period
(Auto precharge)
/CAS latency = 3
t
DAL3
t
DAL2
t
RSC
1CLK
+22.5
1CLK
+20
2
1CLK
+20
1CLK
+20
2
1CLK
+20
1CLK
+20
2
ns
1
/CAS latency = 2
ns
Mode register set cycle time
CLK
Transition time
t
T
0.5
30
0.5
30
1
30
ns
Refresh time (4,096 refresh cycles)
t
REF
64
64
64
ms
Note 1.
The –A75 grade device can satisfy the t
DAL3
spec of 1CLK+20
ns for up to and including 125MHz operation.
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參數(shù)描述
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