參數(shù)資料
型號： UPD45128163G5-A75-9JF
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： PLASTIC, TSOP2-54
文件頁數(shù)： 18/92頁
文件大?。?/td> 682K
代理商： UPD45128163G5-A75-9JF
Data Sheet E0031N30
18
μ
PD45128441, 45128841, 45128163
(3/3)
Notes
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter row active after t
DPL
L
H
H
H
×
NOP
Nop
→
Enter row active after t
DPL
L
H
H
L
×
BST
Nop
→
Enter row active after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter precharge after t
DPL
with auto precharge
L
H
H
H
×
NOP
Nop
→
Enter precharge after t
DPL
L
H
H
L
×
BST
Nop
→
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RC
L
H
H
×
×
NOP/BST
Nop
→
Enter idle after t
RC
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
H
×
×
ACT/PRE/PALL
ILLEGAL
L
L
L
×
×
REF/SELF/MRS
ILLEGAL
Mode register
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RSC
accessing
L
H
H
H
×
NOP
Nop
→
Enter idle after t
RSC
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45128xxx will enter Power down mode.
All input buffers except CKE will be disabled.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45128xxx will enter Self refresh mode. All input
buffers except CKE will be disabled.
Illegal if t
RCD
is not satisfied.
Illegal if t
RAS
is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy t
DPL
.
10.
Illegal if t
RRD
is not satisfied.
2.
3.
4.
Remark
H = High level, L = Low level,
×
= High or Low level (Don’t care), V = Valid data
5.
6.
7.
8.
9.
相關(guān)PDF資料
PDF描述
UPD45128163G5-A75A-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128841G5-A10-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128163G5-A80LI-9JF RAC5-SA(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 15V; Features: AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Approved
UPD45128163G5-A10I-9JF Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes
UPD45128163G5-A10LI-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD45128841G5-A75-9JF 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP
UPD4516161AG5A109NF 制造商:NEC Electronics Corporation 功能描述:
UPD4516161AG5-A10-9NF 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP
UPD4528BC 制造商:Panasonic Industrial Company 功能描述:IC
UPD4528C 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP
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