參數(shù)資料
型號(hào)： UPD45128163G5-A75-9JF
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 32/92頁(yè)
文件大?。?/td> 682K
代理商： UPD45128163G5-A75-9JF
Data Sheet E0031N30
32
μ
PD45128441, 45128841, 45128163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
READ
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
Q1
DQ
Command
Q2
Q3
Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
READ
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1
Q2
Q3
ACT
t
RP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
相關(guān)PDF資料
PDF描述
UPD45128163G5-A75A-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128841G5-A10-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
UPD45128163G5-A80LI-9JF RAC5-SA(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 15V; Features: AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Approved
UPD45128163G5-A10I-9JF Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes
UPD45128163G5-A10LI-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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