- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384043 > UPD45128163G5-A80LI-9JF (ELPIDA MEMORY INC) RAC5-SA(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 15V; Features: AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Approved PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD45128163G5-A80LI-9JF |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | RAC5-SA(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 15V; Features: AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Approved |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 18/86頁(yè) |
| 文件大?。?/td> | 785K |
| 代理商： | UPD45128163G5-A80LI-9JF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)
Data Sheet E0346N10 (Ver. 1.0)
18
μ
PD45128163-I
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100
μ
s or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed.
After the mode register set cycle, t
RSC
(2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1.
The sequence of Mode register programming and Refresh above may be transposed.
2.
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD45128163G5-A10I-9JF | Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Color:Green; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes |
| UPD45128163G5-A10LI-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| UPD4564841G5 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD4564163 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD4564163G5 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD45128841G5-A75-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP |
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| UPD4528BC | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD4528C | 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。