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參數(shù)資料
| 型號： | UPD4564841 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 12/85頁 |
| 文件大小： | 919K |
| 代理商： | UPD4564841 |
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Data Sheet E0149N10
12
μ
PD4564441, 4564841, 4564163
Fig.4 Column address and write
command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
(Bank select)
Col.
Fig.5 Column address and read
command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
(Bank select)
Col.
Fig.6 CBR (auto) refresh command
CLK
Add
A10
A12, A13
(Bank select)
/WE
/CAS
/RAS
/CS
CKE
H
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst write
operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column
address.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During t
RC
period (from refresh command to refresh or activate
command), the
μ
PD4564xxx cannot accept any other command.
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