參數(shù)資料
型號: UPD485505G-35
廠商: NEC Corp.
英文描述: LINE BUFFER 5K-WORD BY 8-BIT
中文描述: 行緩沖區(qū)5K - Word的8位
文件頁數(shù): 15/20頁
文件大小: 174K
代理商: UPD485505G-35
μ
PD485505
15
Data Sheet M10059EJ7V0DS00
Figure 4.4 n-Bit Delay Line Timing Chart (2)
t
WCK
t
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle n–1
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0)
(1)
(2)
(n–2)
(n–1)
(n)
(n+1)
t
DS
t
DH
t
OH
t
AC
(0)
(1)
(n+2)
(n+3)
(2)
(3)
WCK/RCK
(Input)
RSTW
(Input)
D
IN
(Input)
D
OUT
(Output)
Cycle n+1
Cycle 1
Cycle n+2
Cycle 2
Cycle n+3
Cycle 3
t
RH
t
RS
n Cycles
RSTR
(Input)
Cycle n
Cycle 0
Write
Read
t
WAR
Remark
RE, WE = “L” level
Figure 4.5 n-Bit Delay Line Timing Chart (3)
t
WCK
t
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle n–1
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0)
(1)
(2)
(n–2)
(n–1)
(n)
(n+1)
t
DS
t
DH
t
OH
t
AC
(0)
(1)
(n+2)
(n+3)
(2)
(3)
WCK/RCK
(Input)
RSTW/
RSTR
(Input)
D
IN
(Input)
D
OUT
(Output)
Cycle n+1
Cycle 1
Cycle n+2
Cycle 2
Cycle n+3
Cycle 3
t
REH
n Cycles
RE
(Input)
t
REN2
Cycle n
Cycle 0
Write
Read
t
WAR
High impedance
Remark
WE = “L” level
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