- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384043 > UPD485505G-35 (NEC Corp.) LINE BUFFER 5K-WORD BY 8-BIT PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD485505G-35 |
| 廠商： | NEC Corp. |
| 英文描述： | LINE BUFFER 5K-WORD BY 8-BIT |
| 中文描述： | 行緩沖區(qū)5K - Word的8位 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | UPD485505G-35 |
μ
PD485505
5
Data Sheet M10059EJ7V0DS00
2. Operation Mode
μ
PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.
When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which
the WCK rising edge is in the WE = “H” level (t
WEW
). The WCK does not increment the write address pointer
at this time.
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
incrementing again.
2.2 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input
and data is output after t
AC
. Refer to Read Cycle Timing Chart.
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
the RCK rising edge is in the RE = “H” level (t
REW
). The RCK does not increment the read address pointer at
this time.
2.3 Write Reset Cycle/Read Reset Cycle
After power up, the
μ
PD485505 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark
Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD4990A | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| UPD4990AC | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| UPD4990AG | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| UPD63210 | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
| UPD63210GT | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD485505G-35-A | 制造商:Renesas Electronics 功能描述:25ns 5V Cut Tape |
| UPD485506G5-25-7JF | 制造商:NEC Electronics Corporation 功能描述: 制造商:NEC Electronics Corporation 功能描述:FIELD/FRAME/LINE MEMORY, 44 Pin, Plastic, TSOP |
| UPD485506G5-25-7JF-A | 制造商:Renesas Electronics 功能描述:18ns 5V Cut Tape |
| UPD48576218FF-E24-DW1-A | 制造商:Renesas Electronics Corporation 功能描述:UPD48576218FF-E24-DW1-A - Trays |
| UPD4990AG-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。