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參數(shù)資料
| 型號： | UPD4991AGS |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT PARALLEL I/O CALENDAR CLOCK |
| 中文描述： | 4位并行I / O日歷鐘 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 133K |
| 代理商： | UPD4991AGS |
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μ
PD4991A
14
Table 3 Data Correspondence Table 1
CONTROL REGISTER1 (TIME COUNTER CONTROL)
ADDRESS = (1, 1, 0, 1)
D3
D2
D1
D0
W/O
0
NOP
RUN
NOP
NOP
1
CLOCK WAIT
*4
CLOCK STOP
*3
ADJUST (+/–)30 s
*1
RESET
*2
*1.
ADJUST (+/–)30 s
Second digit
00 to 29
→
00 (second)
30 to 59
→
00 (second) + 1 (minute)
The BUSY flag remains set until a carry occurs.
In MODE (0, *, 0, 0), stages 10 to 15 of the 15-stage divider are reset.
In MODE (0, *, 1, 1), all the stages of the 15-stage divider are reset.
*2.
RESET
In MODE (0, *, 0, 0), stages 10 to 15 of the 15-stage divider are reset.
In MODE (0, *, 1, 1), all the stages of the 15-stage divider are reset.
*3.
CLOCK STOP
This command is used to write time.
To set time, execute the CLOCK RESET command and then the CLOCK STOP command. Then write
the time data. If the data is written without the clock stopped, the correct value may not be set.
*4.
CLOCK WAIT
This command is used to read time.
When 1 is written to this bit, the clock is stopped. If the CLOCK RUN command is executed within 0.5
second, no delay in respect to the actual time occurs.
Table 4 Data Correspondence Table 2
CONTROL REGISTER2 (TP
1
/TP
2
CONTROL)
ADDRESS = (1, 1, 1, 0)
D3
D2
D1
D0
ALARM setting
Alarm coincidence
Output status
0
forced output flag
(TP
1
)
0: ENABLE
0: RESET
0: ENABLE
W/O
1: DISABLE
1: SET
1: DISABLE
1
INTERVAL CLOCK
INTERVAL COUNTER
Output status
(TP
2
)
0: RUN
0: NOP
0: ENABLE
1: CLK STOP
1: RESET
1: DISABLE
BUSY flag
Alarm coincidence flag
Interval flag
R/O
*
0: OFF
0: OFF
0: OFF
1: ON
1: ON
1: ON
*: Don’t Care
R/O : READ ONLY
W/O : WRITE ONLY
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