- 您現在的位置：買賣IC網 > PDF目錄378739 > UPD65345 CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] PDF資料下載
參數資料
| 型號： | UPD65345 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設計手冊[05/2003] |
| 文件頁數： | 17/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65345 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
17
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
3.2.4 S
2
port (bit 1 of P1)
The S
2
port is an input port.
Use of the STOP mode release of the S
2
port can be specified by bit 3 of the P4 register.
When using the pin as a key input from a key matrix, enable (bit 3 of P4 register is set to 1) the use of the STOP
mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled
(bit 3 of P4 register is set to 0), it can be used as the input port which does not release the STOP mode even if
the release condition is established (at this time, a pull-down resistor is not connected internally.)
The state of the pin can be read in both cases.
At reset, the pin is set to INPUT mode where the STOP mode release is disabled, and goes to high-impedance
state.
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0000 0011B.
Table 3-4. Control Register 0 (P3)
Bit
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Name
—
DP (Data pointer)
DP
10
Note
DP
9
TCTL
CARY
MOD
1
MOD
0
DP
8
Set
0
Fixed
0
0
0
1/1
ON
Refer to
Table 3-5
.
value
1
to “0”
1
1
1
1/2
OFF
When reset0
0
0
0
0
0
0
1
1
b
0
, b
1
: These bits specify the carrier frequency and duty ratio of the REM output.
b
2
: This bit specifies the availability of the carrier of the frequency specified by b
0
and b
1
.
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
b
3
: This bit changes the carrier frequency and the timer clock’s frequency division ratio.
“0” = 1/1 (carrier frequency: the specified value of b
0
and b
1
; timer clock: f
X
/64)
“1” = 1/2 (carrier frequency: half of the specified value of b
0
and b
1
; timer clock: f
X
/128)
Table 3-5. Timer Clock and Carrier Frequency Setup
b
3
b
2
b
1
b
0
Timer Clock
Carrier Frequency (Duty Ratio)
0
0
0
0
f
X
/64
f
X
/8 (Duty 1/2)
0
1
f
X
/64 (Duty 1/2)
1
0
f
X
/96 (Duty 1/2)
1
1
f
X
/96 (Duty 1/3)
1
×
×
Without carrier (high level)
0
0
0
0
f
X
/128
f
X
/16 (Duty 1/2)
0
1
f
X
/128 (Duty 1/2)
1
0
f
X
/192 (Duty 1/2)
1
1
f
X
/192 (Duty 1/3)
1
×
×
Without carrier (high level)
b
4
, b
5
, b
6
: These bits specify the high-order 3 bits (DP
8
, DP
9
and DP
10
) of ROM’s data pointer.
Note
Set DP
10
of the
μ
PD64A to "0".
Remark
×
: don’t care
相關PDF資料 |
PDF描述 |
|---|---|
| UPD65346 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65347 | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| UPD65348 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65349 | CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65350 | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UPD65346 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65347 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| UPD65348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65349 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-10HD Family Pamphlet | Pamphlet[07/2003] |
| UPD65350 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
發(fā)布緊急采購，3分鐘左右您將得到回復。