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參數(shù)資料
| 型號(hào)： | UPD6P4BGS |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION |
| 中文描述： | 4位單片機(jī)的紅外遙控傳輸 |
| 文件頁(yè)數(shù)： | 19/32頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | UPD6P4BGS |
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Data Sheet U13594EJ2V0DS00
19
μ
PD6P4B
AC Programming Characteristics (T
A
= 25
°
C, V
DD
= 6.0
±
0.25 V, V
PP
= 12.5
±
0.3 V)
Parameter
Symbol
Note1
Test Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
(vs. MD
0
↓
)
MD
1
setup time (vs. MD
0
↓
)
Data setup time (vs. MD
0
↓
)
Address hold time
Note 2
(vs. MD
0
↑
)
Data hold time (vs. MD
0
↑
)
MD
0
↑→
data output float delay time
V
PP
setup time (vs. MD
3
↑
)
V
DD
setup time (vs. MD
3
↑
)
t
AS
t
AS
2
μ
s
μ
s
μ
s
μ
s
μ
s
t
M1S
t
OES
2
t
DS
t
DS
2
t
AH
t
AH
2
t
DH
t
DH
2
t
DF
t
DF
0
130
ns
t
VPS
t
VPS
2
μ
s
μ
s
t
VDS
t
VCS
2
Initial program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
MD
0
setup time (vs. MD
1
↑
)
MD
0
↓→
data output delay time
MD
1
hold time (vs. MD
0
↑
)
MD
1
recovery time (vs. MD
0
↓
)
t
MOS
t
CES
2
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
MHz
t
DV
t
DV
MD0 = MD1 = V
IL
1
t
M1H
t
OEH
t
M1H
+t
M1R
≥
50
μ
s
2
t
M1R
t
OR
2
Program counter reset time
t
PCR
–
10
CLK input high-, low-level width
t
XH
, t
XL
–
0.125
CLK input frequency
f
X
–
8
Initial mode set time
t
I
–
2
μ
s
μ
s
μ
s
μ
s
μ
s
ns
MD
3
setup time (vs. MD
1
↑
)
MD
3
hold time (vs. MD
1
↓
)
MD
3
setup time (vs. MD
0
↓
)
Address
Note 2
→
data output delay time
Address
Note 2
→
data output hold time
MD
3
hold time (vs. MD
0
↑
)
MD
3
↓→
data output float delay time
Reset setup time
t
M3S
–
2
t
M3H
–
2
t
M3SR
–
When program memory is read
2
t
OAD
t
ACC
When program memory is read
2
t
HAD
t
OH
When program memory is read
0
130
t
M3HR
–
When program memory is read
2
μ
s
μ
s
μ
s
t
DFR
–
When program memory is read
2
t
RES
–
10
Oscillation stabilization wait time
Note 3
t
WAIT
–
2
ms
Notes 1.
Equivalent symbol of the corresponding
μ
PD27C256A (The
μ
PD27C256A is a maintenance product.)
2.
The internal address signal is incremented at the falling edge of the third clock of CLK.
3.
Connect a 4 MHz ceramic resonator between the X
IN
and X
OUT
pins.
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