參數(shù)資料
型號: UPD70208H
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 57/110頁
文件大?。?/td> 625K
代理商: UPD70208H
5
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
2
2-4
2
2-4
3
3-5
7 6 5 4 3 2 1 0
CY
reg LSB, reg
reg
÷
2
reg MSB
CY
reg MSB
bit after reg MSB : V
1
reg MSB = bit after reg MSB : V
0
CY
(mem) LSB, (mem)
(mem)
÷
2
(mem) MSB
CY
(mem) MSB
bit after (mem) MSB
(mem) MSB = bit after (mem) MSB
: V
1
: V
0
temp
CL, while CL
0 the following operations are repeated:
CY
reg LSB, reg
reg
÷
2
reg MSB
CY
temp
temp – 1
temp
CL, while CL
0 the following operations are repeated:
CY
(mem) LSB,(mem)
(mem)
÷
2
(mem) MSB
CY
temp
temp – 1
temp
imm8, while CL
0 the following operations are
repeated:
CY
reg LSB,reg
reg
÷
2
reg MSB
CY
temp
temp – 1
temp
imm8, while CL
0 the following operations are
repeated:
CY
(mem) LSB,(mem)
(mem)
÷
2
(mem) MSB
CY
temp
temp – 1
6
13/21
7 + n
16/24
+ n
7 + n
16/24
+ n
ROR
reg, 1
mem, 1
reg, CL
mem, CL
reg, imm8
mem, imm8
1 1 0 0 1 reg
mod
0 0 1 mem
1 1 0 0 1 reg
mod
0 0 1 mem
1 1 0 0 1 reg
mod
0 0 1 mem
×
×
×
×
×
U
×
U
×
U
×
U
Clock Cycles
V40HL V50HL
6
13/21
7 + n
16/24
+ n
7 + n
16/24
+ n
n: Number of shifts
R
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