參數(shù)資料
型號： UPD70208H
廠商： NEC Corp.
英文描述： V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述： V40HLTM，V50HLTM 16 / 8，16位微處理器
文件頁數(shù)： 80/110頁
文件大?。?/td> 625K
代理商： UPD70208H
80
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
MIN.
MAX.
External clock input cycle
External clock input high-level width (V
KH
=0.8 V
DD
)
External clock input low-level width (V
KL
=0.2 V
DD
)
External clock input rise time (0.2 V
DD
→
0.8 V
DD
)
External clock input fall time (0.8 V
DD
→
0.2 V
DD
)
Clock output cycle
Clock output high-level width (V
OH
=0.7 V
DD
)
Clock output low-level width (V
OL
=0.2 V
DD
)
Clock output rise time (0.2 V
DD
→
0.7 V
DD
)
Clock output fall time (0.7 V
DD
→
0.2 V
DD
)
CLKOUT delay time (vs. external clock)
Input rise time (except external clock) (0.2 V
DD
→
0.7 V
DD
)
Input fall time (except external clock) (0.7 V
DD
→
0.2 V
DD
)
Output rise time (except CLKOUT) (0.2 V
DD
→
0.7 V
DD
)
Output fall time (except CLKOUT) (0.7 V
DD
→
0.2 V
DD
)
RESET setup time (vs. CLKOUT
↓
)
Note 1
RESET hold time (vs. CLKOUT
↓
)
Note 1
RESOUT output delay time (vs. CLKOUT
↓
)
READY inactive setup time (vs. CLKOUT
↑
)
READY inactive hold time (vs. CLKOUT
↑
)
READY active setup time (vs. CLKOUT
↑
)
READY active hold time (vs. CLKOUT
↑
)
NMI setup time (vs. CLKOUT
↑
)
POLL setup time (vs. CLKOUT
↑
)
Data setup time (vs. CLKOUT
↓
)
Data hold time (vs. CLKOUT
↓
)
CLKOUT
→
address delay time
Note 2
CLKOUT
→
address hold time
CLKOUT
↓ →
PS delay time
CLKOUT
↓ →
PS float delay time
Address setup time (vs. ASTB
↓
)
CLKOUT
↓ →
address float delay time
Note 3
CLKOUT
↓ →
ASTB
↑
delay time
CLKOUT
↑ →
ASTB
↓
delay time
ASTB high-level width
(2)
μ
PD70208H, 70216H-20 (T
A
= –40 to +85
°
C, V
DD
= 3 V
±
10%) (1/3)
Output Pin Load Capacitance: C
L
= 100 pF
μ
PD70208H-20
μ
PD70216H-20
Unit
Parameter
Symbol
t
CYX
50
DC
ns
t
XXH
19
ns
t
XXL
19
ns
t
XR
5
ns
t
XF
5
ns
t
CYK
100
DC
ns
t
KKH
0.5t
CYK
–7
ns
t
KKL
0.5t
CYK
–7
ns
t
KR
7
ns
t
KF
7
ns
t
DXK
45
ns
t
IR
15
ns
t
IF
10
ns
t
OR
15
ns
t
OF
10
ns
t
SRESK
25
ns
t
HKRES
25
ns
t
DKRES
5
50
ns
t
SRYLK
15
ns
t
HKRYL
20
ns
t
SRYHK
15
ns
t
HKRYH
20
ns
t
SNMIK
15
ns
t
SPOLK
20
ns
t
SDK
15
ns
t
HKD
5
ns
t
DKA
5
50
ns
t
HKA
5
ns
t
DKP
5
50
ns
t
FKP
5
50
ns
t
SAST
t
KKL
–20
ns
t
FKA
t
HKA
50
ns
t
DKSTH
40
ns
t
DKSTL
45
ns
t
STST
t
KKL
–10
ns
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
Notes 1.
When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.
2.
Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,
BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
3.
Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,
IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
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