參數(shù)資料
型號(hào): UPD70208HGK-12-9EU
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁(yè)數(shù): 39/110頁(yè)
文件大?。?/td> 625K
代理商: UPD70208HGK-12-9EU
39
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
The instruction set is shown in tabular form on the following pages.
Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the
following conditions.
Prefetch time and wait time for using bus, etc. are not included.
0 wait is assumed for memory access. That is, the clock number of one bus cycle is four clock cycle.
0 wait is assumed for I/O access.
Primitive block transfer instruction and primitive input/output instruction is included repeat prefixes.
The number of clock cycle of instruction with byte processing and word processing (with W bit) is shown as the followings.
(1) V40HL
On the left of "/"
:
The value corresponding to byte processing (W= 0) or word processing (W = 1) of even
address
On the right of "/": The value corresponding to word processing (W =1) of odd address
For the clock of block transfer related instruction of V40HL, see
Table 15-8
.
Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL)
Instruction
Number of Clock Cycles
Byte Processing (W = 0)
Word Processing (W = 1)
MOVBK
9 + 8
×
rep
(9)
9 + 16
×
rep
(17)
CMPBK
7 + 14
×
rep
(13)
7 + 22
×
rep
(21)
CMPM
7 + 10
×
rep
(7)
7 + 14
×
rep
(11)
LDM
7 + 9
×
rep
(7)
7 + 13
×
rep
(11)
STM
5 + 4
×
rep
(5)
5 + 8
×
rep
(9)
INM
9 + 8
×
rep
(10)
9 + 16
×
rep
(18)
OUTM
9 + 8
×
rep
(10)
9 + 16
×
rep
(18)
Remark
The figures in parentheses apply to one-time processing only.
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