參數(shù)資料
型號(hào): UPD70208HGK-12-9EU
廠(chǎng)商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁(yè)數(shù): 77/110頁(yè)
文件大?。?/td> 625K
代理商: UPD70208HGK-12-9EU
77
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
AC CHARACTERISTICS
(1)
μ
PD70208H, 70216H-10/12/16 (T
A
= –40 to +85
°
C, V
DD
= 3 V
±
10%) (1/3)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
External clock input cycle
External clock input high-level width (V
KH
=0.8 V
DD
)
External clock input low-level width (V
KL
=0.2 V
DD
)
External clock input rise time (0.2 V
DD
0.8 V
DD
)
External clock input fall time (0.8 V
DD
0.2 V
DD
)
Clock output cycle
Clock output high-level width (V
OH
=0.7 V
DD
)
Clock output low-level width (V
OL
=0.2 V
DD
)
Clock output rise time (0.2 V
DD
0.7 V
DD
)
Clock output fall time (0.7 V
DD
0.2 V
DD
)
CLKOUT delay time (vs. external clock)
Input rise time (except external clock) (0.2 V
DD
0.7 V
DD
)
Input fall time (except external clock) (0.7 V
DD
0.2 V
DD
)
Output rise time (except CLKOUT) (0.2 V
DD
0.7 V
DD
)
Output fall time (except CLKOUT) (0.7 V
DD
0.2 V
DD
)
RESET setup time (vs. CLKOUT
)
Note 1
RESET hold time (vs. CLKOUT
)
Note 1
RESOUT output delay time (vs. CLKOUT
)
READY inactive setup time (vs. CLKOUT
)
READY inactive hold time (vs. CLKOUT
)
READY active setup time (vs. CLKOUT
)
READY active hold time (vs. CLKOUT
)
NMI setup time (vs. CLKOUT
)
POLL setup time (vs. CLKOUT
)
Data setup time (vs. CLKOUT
)
Data hold time (vs. CLKOUT
)
CLKOUT
address delay time
Note 2
CLKOUT
address hold time
CLKOUT
↓ →
PS delay time
CLKOUT
↓ →
PS float delay time
Address setup time (vs. ASTB
)
CLKOUT
↓ →
address float delay time
Note 3
CLKOUT
↓ →
ASTB
delay time
CLKOUT
↑ →
ASTB
delay time
ASTB high-level width
Output Pin Load Capacitance: C
L
= 100 pF
μ
PD70208H-10
μ
PD70216H-10
μ
PD70208H-16
μ
PD70216H-16
μ
PD70208H-12
μ
PD70216H-12
Unit
Symbol
Parameter
Notes 1.
When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.
2.
Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,
BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
3.
Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,
IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
t
CYX
100
DC
83
DC
62.5
DC
ns
t
XXH
40
30
20
ns
t
XXL
40
30
20
ns
t
XR
10
10
10
ns
t
XF
10
10
10
ns
t
CYK
200
DC
166
DC
125
DC
ns
t
KKH
0.5t
CYK
–7
0.5t
CYK
–7
0.5t
CYK
–7
ns
t
KKL
0.5t
CYK
–7
0.5t
CYK
–7
0.5t
CYK
–7
ns
t
KR
7
7
7
ns
t
KF
7
7
7
ns
t
DXK
75
65
55
ns
t
IR
20
20
20
ns
t
IF
12
12
12
ns
t
OR
20
20
20
ns
t
OF
12
12
12
ns
t
SRESK
25
25
25
ns
t
HKRES
35
35
35
ns
t
DKRES
5
80
5
70
5
60
ns
t
SRYLK
20
20
15
ns
t
HKRYL
30
30
25
ns
t
SRYHK
20
20
15
ns
t
HKRYH
30
30
25
ns
t
SNMIK
15
15
15
ns
t
SPOLK
20
20
20
ns
t
SDK
20
20
15
ns
t
HKD
5
5
5
ns
t
DKA
5
75
5
65
5
55
ns
t
HKA
5
5
5
ns
t
DKP
5
80
5
70
5
60
ns
t
FKP
5
80
5
70
5
60
ns
t
SAST
t
KKL
–30
t
KKL
–30
t
KKL
–30
ns
t
FKA
5
80
5
70
5
60
ns
t
DKSTH
5
65
5
55
5
45
ns
t
DKSTL
5
70
5
60
5
50
ns
t
STST
t
KKL
–10
t
KKL
–10
t
KKL
–10
ns
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