參數(shù)資料
型號: UPD70208HGK-20-9EU
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 24/110頁
文件大?。?/td> 625K
代理商: UPD70208HGK-20-9EU
24
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
4.
CG (CLOCK GENERATOR)
The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1
and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output.
The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a
system I/O area register.
Figure 4-1. Internal Block Diagram of CG
5.
BIU (BUS INTERFACE UNIT)
The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control
unit) and REFU (refresh control unit).
The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock
generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also
output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU.
Figure 5-1. RESET and READY Signal Synchronization
X1
X2
CPU, DMAU, REFU, SCU
CLKOUT
Baud Rate Counter (BRC)
TCU
Oscillator
Divide-by-1-to-8
Scaler
Divide-by-2-to-16
Scaler
Divide-by-2
Scaler
f
XX
f
X
Q
D
CK
Q
D
CK
Q
D
CK
RESET
READY
CLOCK
RESOUT
To Internal Units
To Internal Units
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