參數(shù)資料
型號： UPD70208HLP-20
廠商： NEC Corp.
英文描述： V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述： V40HLTM，V50HLTM 16 / 8，16位微處理器
文件頁數(shù)： 64/110頁
文件大?。?/td> 625K
代理商： UPD70208HLP-20
6
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
1 1 0 0 1 1 0 0
1 1 0 0 1 1 0 1
1 1 0 0 1 1 1 0
1 1 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 1 1 0 0 0 1 0
1
2
1
1
3
2-4
7 6 5 4 3 2 1 0
TA
←
(00DH, 00CH), TC
←
(00FH, 00EH)
SP
←
SP – 2, (SP + 1, SP)
←
PSW, IE
←
0, BRK
←
0
SP
←
SP – 2, (SP + 1, SP)
←
PS, PS
←
TC
SP
←
SP – 2, (SP + 1, SP)
←
PC, PC
←
TA
TA
←
(4 n + 1, 4n), TC
←
(4n + 3, 4n + 2) n = imm8
SP
←
SP – 2, (SP + 1, SP)
←
PSW, IE
←
0, BRK
←
0
SP
←
SP – 2, (SP + 1, SP)
←
PS, PS
←
TC
SP
←
SP – 2, (SP + 1, SP)
←
PC, PC
←
TA
If V = 1
TA
←
(011H, 010H), TC
←
(013H, 012H)
SP
←
SP – 2, (SP + 1, SP)
←
PSW, IE
←
0, BRK
←
0
SP
←
SP – 2, (SP + 1, SP)
←
PS, PS
←
TC
SP
←
SP – 2, (SP + 1, SP)
←
PC, PC
←
TA
PC
←
(SP + 1, SP), PS
←
(SP + 3, SP + 2),
PSW
←
(SP + 5, SP + 4), SP
←
SP + 6
TA
←
(4 n + 1, 4n), TC
←
(4n + 3, 4n + 2) n = imm8
SP
←
SP – 2, (SP + 1, SP)
←
PSW, MD
←
0
MD is set to write enabled
SP
←
SP – 2, (SP + 1, SP)
←
PS, PS
←
TC
SP
←
SP – 2, (SP + 1, SP)
←
PC, PC
←
TA
If (mem32) > reg16 or (mem32 + 2) < reg16
TA
←
(015H, 014H), TC
←
(017H, 016H)
SP
←
SP – 2, (SP + 1, SP)
←
PSW, IE
←
0, BRK
←
0
SP
←
SP – 2, (SP + 1, SP)
←
PS, PS
←
TC
SP
←
SP – 2, (SP + 1, SP)
←
PC, PC
←
TA
50
50
Note 1
39
50
Note 3
I
BRK
BRKV
RETI
BRKEM
CHKIND
3
imm8
( = 3)
imm8
reg16, mem32
1 1 1 1 1 1 1 1
mod reg mem
R
R
R
R
R
R
Notes 1.
When V = 1: 52
When V = 0: 3
When V = 1: 40/52
When V = 0: 3
When interrupt condition is established
When interrupt condition is not established
When interrupt condition is established
When interrupt condition is not established
2.
3.
: 72 to 75
: 25
: (52 to 55)/(72 to 75)
: 17/25
4.
Clock Cycles
V40HL V50HL
38/50
38/50
Note 2
27/39
38/50
Note 4
相關(guān)PDF資料
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