參數(shù)資料
型號: UPD70216HGF-12-3B9
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 68/110頁
文件大小: 625K
代理商: UPD70216HGF-12-3B9
68
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
AC CHARACTERISTICS
(1)
μ
PD70208H, 70216H-10/12/16 (T
A
= –40 to +85
°
C, V
DD
= 5 V
±
10%) (1/3)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
External clock input cycle
External clock input high-level width (V
KH
=3.0 V)
External clock input low-level width (V
KL
=1.5 V)
External clock input rise time (1.5
3.0 V)
External clock input fall time (3.0
1.5 V)
Clock output cycle
Clock output high-level width (V
OH
=3.0 V)
Clock output low-level width (V
OL
=1.5 V)
Clock output rise time (1.5
3.0 V)
Clock output fall time (3.0
1.5 V)
CLKOUT delay time (vs. external clock)
Input rise time (except external clock) (0.8
2.2 V)
Input fall time (except external clock) (2.2
0.8 V)
Output rise time
(except CLKOUT) (0.8
2.2 V)
E, P, X, M masks
Others
Output fall time (except CLKOUT) (2.2
0.8 V)
RESET setup time (vs. CLKOUT
)
Note 1
RESET hold time (vs. CLKOUT
)
Note 1
RESOUT output delay time (vs. CLKOUT
)
READY inactive setup time (vs. CLKOUT
)
READY inactive hold time (vs. CLKOUT
)
READY active setup time (vs. CLKOUT
)
READY active hold time (vs. CLKOUT
)
NMI setup time (vs. CLKOUT
)
POLL setup time (vs. CLKOUT
)
Data setup time (vs. CLKOUT
)
Data hold time (vs. CLKOUT
)
CLKOUT
address delay time
Note 2
CLKOUT
address hold time
CLKOUT
↓ →
PS delay time
CLKOUT
↓ →
PS float delay time
Address setup time (vs. ASTB
)
CLKOUT
↓ →
address float delay time
Note 3
CLKOUT
↓ →
ASTB
delay time
Output Pin Load Capacitance: C
L
= 100 pF
μ
PD70208H-10
μ
PD70216H-10
μ
PD70208H-16
μ
PD70216H-16
μ
PD70208H-12
μ
PD70216H-12
Notes 1.
When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.
2.
Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,
BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
3.
Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,
IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
Unit
Symbol
Parameter
t
CYX
50
DC
40
DC
31.25
DC
ns
t
XXH
19
14
12
ns
t
XXL
19
14
12
ns
t
XR
5
5
5
ns
t
XF
5
5
5
ns
t
CYK
100
DC
80
DC
62.5
DC
ns
t
KKH
0.5t
CYK
–5
0.5t
CYK
–5
0.5t
CYK
–5
ns
t
KKL
0.5t
CYK
–5
0.5t
CYK
–5
0.5t
CYK
–5
ns
t
KR
5
5
5
ns
t
KF
5
5
5
ns
t
DXK
40
35
20
ns
t
IR
15
15
15
ns
t
IF
10
10
10
ns
t
OR
15
15
15
ns
10
10
10
ns
t
OF
10
10
10
ns
t
SRESK
20
20
20
ns
t
HKRES
25
25
15
ns
t
DKRES
5
50
5
40
5
30
ns
t
SRYLK
15
10
7
ns
t
HKRYL
20
15
15
ns
t
SRYHK
15
10
7
ns
t
HKRYH
20
20
15
ns
t
SNMIK
15
15
15
ns
t
SPOLK
20
20
20
ns
t
SDK
15
10
7
ns
t
HKD
5
5
5
ns
t
DKA
5
50
5
40
5
28
ns
t
HKA
5
5
5
ns
t
DKP
5
50
5
40
5
30
ns
t
FKP
5
50
5
40
5
30
ns
t
SAST
t
KKL
–20
t
KKL
–10
t
KKL
–10
ns
t
FKA
t
HKA
50
t
HKA
40
t
HKA
30
ns
t
DKSTH
40
30
25
ns
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