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參數(shù)資料
| 型號(hào)： | UPD703015AYGC |
| 廠商： | NEC Corp. |
| 英文描述： | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | V850/SA1TM 32-/16-BIT單片機(jī) |
| 文件頁數(shù)： | 31/48頁 |
| 文件大小： | 309K |
| 代理商： | UPD703015AYGC |
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Data Sheet U14526EJ2V0DS00
31
μ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Asynchronous)
(T
A
= –40 to +85°C, V
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= BV
SS
= 0 V, Output pin load capacitance: C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓
)
t
SAST
<13>
0.5T
– 15
ns
Address hold time (from ASTB
↓
)
t
HSTA
<14>
0.5T
– 15
ns
Address float from DSTB
↓
t
FDA
<15>
2
ns
Data input setup time from address
t
SAID
<16>
(2 + n)T – 25
ns
Data input setup time from DSTB
↓
t
SDID
<17>
(1 + n)T – 25
ns
Delay time from ASTB
↓
to DSTB
↓
t
DSTD
<18>
0.5T
– 15
ns
Data input hold time (from DSTB
↑
)
t
HDID
<19>
0
ns
Address output time from DSTB
↑
t
DDA
<20>
(1 + i)T – 15
ns
Delay time from DSTB
↑
to ASTB
↑
t
DDST1
<21>
0.5T – 15
ns
Delay time from DSTB
↑
to ASTB
↓
t
DDST2
<22>
(1.5 + i)T – 15
ns
DSTB low-level width
t
WDL
<23>
(1 + n)T – 15
ns
ASTB high-level width
t
WSTH
<24>
T – 15
ns
Data output time from DSTB
↓
t
DDOD
<25>
15
ns
Data output setup time (to DSTB
↑
)
t
SODD
<26>
(1 + n)T – 20
ns
Data output hold time (from DSTB
↑
)
t
HDOD
<27>
T – 15
ns
t
SAWT1
<28>
n
≥
1
1.5T – 25
ns
WAIT setup time (to address)
t
SAWT2
<29>
n
≥
1
(1.5 + n)T – 25
ns
t
HAWT1
<30>
n
≥
1
(0.5 + n)T
ns
WAIT hold time (from address)
t
HAWT2
<31>
n
≥
1
(1.5 + n)T
ns
t
SSTWT1
<32>
n
≥
1
T – 25
ns
WAIT setup time (to ASTB
↓
)
t
SSTWT2
<33>
n
≥
1
(1 + n)T – 25
ns
t
HSTWT1
<34>
n
≥
1
nT
ns
WAIT hold time (from ASTB
↓
)
t
HSTWT2
<35>
n
≥
1
(1 + n)T
ns
HLDRQ high-level width
t
WHQH
<36>
T + 10
ns
HLDAK low-level width
t
WHAL
<37>
T – 15
ns
Bus output delay time from HLDAK
↑
t
DHAC
<38>
0
ns
Delay time from HLDRQ
↓
to HLDAK
↓
t
DHQHA1
<39>
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑
to HLDAK
↑
t
DHQHA2
<40>
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU operation clock frequency)
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
i: Number of idle states inserted after the read cycle (0 or 1).
The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
2.
3.
4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD703015AGC | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014A | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AF1 | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AGC | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD703014AY | V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER |
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|---|---|
| UPD703015B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
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| UPD703015BY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
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| UPD703015Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
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