
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
User
’
s Manual U15862EJ3V0UD
508
(4) Divisor selection register n (BRGCAn)
This is an 8-bit register used to control the serial transfer speed (divisor of CSIA clock).
This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial
status register n (CSISn) is 1, rewriting the BRGCAn register is prohibited.
7
0
BRGCn1
0
0
1
1
BRGCn0
0
1
0
1
Selection of CSIAn serial clock (f
SCKA
division ratio)
BRGCAn
6
0
5
0
4
0
3
0
2
0
1
BRGCn1
0
BRGCn0
After reset: 03H R/W Address: FFFFFD43H, FFFFD53H
6 (f
SCKA
/6)
8 (f
SCKA
/8)
16 (f
SCKA
/16)
32 (f
SCKA
/32)
Remark
n = 0 (V850ES/KF1)
n = 0, 1 (V850ES/KG1, V850ES/KJ1)
(5) Automatic data transfer address point specification register n (ADTPn)
This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data
transfer the ATEn bit of serial operation mode specification register n (CSIMAn) = 1).
This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial
status register n (CSISn) is 1, rewriting the ADTPn register is prohibited.
In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer
RAM are incorporated.
Example
When the ADTPn register is set to 07H
8 bytes of 00H to 07H are transferred.
In repeat transfer mode (ATMn bit of CSIMAn register = 1), transfer is performed repeatedly up to the
address value set in ADTPn.
Example
When 07H is transferred to ADTPn (repeat transfer mode)
Transfer is repeated as 00H to 07H, 00H to 07H,
…
.
7
0
ADTPn
6
0
5
0
4
ADTPn4
3
ADTPn3
2
ADTPn2
1
ADTPn1
0
ADTPn0
After reset: 00H R/W Address: FFFFFD44H, FFFFD54H
Caution
Be sure to set bits 5 to 7 to 0.
Remark
n = 0 (V850ES/KF1)
n = 0, 1 (V850ES/KG1, V850ES/KJ1)