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參數資料
| 型號： | uPD720114GA-YEU-A |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數： | 23/32頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD720114GA-YEU-A |
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Data Sheet S17462EJ4V0DS
23
μ
PD720114
Timing Diagram
Figure 2-11. Hub Differential Delay, Differential Jitter, and SOP Distortion
C. Upstream Hub Delay with or without Cable
D. Measurement Points
50% Point of
Initial Swing
50% Point of
Initial Swing
Upstream
End of
Cable
Upstream
Port of Hub
Downstream
Port of Hub
Downstream
Port of Hub
Downstream
Port of Hub
Upstream Port
or
End of Cable
A. Downstream Hub Delay with Cable
B. Downstream Hub Delay without Cable
Hub Delay
Downstream
t
HDD1
Hub Delay
Upstream
t
HDD1
t
HDD2
Crossover
Point
Crossover
Point
Crossover
Point
V
SS
Hub Differential Jitter:
t
HDJ1
= t
HDDx
(J)
t
HDDx
(K) or t
HDDx
(K)
t
HDDx
(J) Consecutive Transitions
t
HDJ2
= t
HDDx
(J)
t
HDDx
(J) or t
HDDx
(K)
t
HDDx
(K) Paired Transitions
Bit after SOP Width Distortion (same as data jitter for SOP and next J transition):
t
FSOP
= t
HDDx
(next J)
t
HDDx
(SOP)
Low-speed timings are determined in the same way for:
t
LHDD
, t
LDHJ1
, t
LDJH2
, t
LUHJ1
, t
LUJH2
, and t
LSOP
Host or
Hub
Hub
Function
Upstream end of cable
Upstream port
Downstream port
Downstream signaling
Upstream signaling
Plug
Receptacle
Hub Delay
Downstream
t
HDD2
V
SS
V
SS
V
SS
V
SS
V
SS
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| UPD720114GA-YEU-ATR | 制造商:Renesas Electronics Corporation 功能描述:I/O CNTRLR USB CNTRLR 48TQFP - Trays |
| UPD720114K9-4E4-A | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 HUB CTRL, 4-PORTS, 40-PIN PLASTIC QFN (6MMX6MM) - Trays |
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