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參數(shù)資料
| 型號： | uPD720114GA-YEU-A |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD720114GA-YEU-A |
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Data Sheet S17462EJ4V0DS
8
μ
PD720114
2.2
Terms Used in Absolute Maximum Ratings
Terminology
Parameter
Symbol
Meaning
Power supply voltage
V
DD33
,
V
DD33REG
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to a V
DD
pin.
Input voltage
V
I
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an input pin.
Output voltage
V
O
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an output pin.
Output current
I
O
Indicates absolute tolerance values for DC current to prevent damage or
reduced reliability when current flows out of or into an output pin.
Operating temperature
T
A
Indicates the ambient temperature range for normal logic operations.
Storage temperature
T
stg
Indicates the element temperature range within which damage or reduced
reliability will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter
Symbol
Meaning
Power supply voltage
V
DD33
,
V
DD33REG
Indicates the voltage range for normal logic operations to occur when V
SS
= 0
V.
High-level input voltage
V
IH
Indicates the voltage, applied to the input pins of the device, which indicates
the high level state for normal operation of the input buffer.
* If a voltage that is equal to or greater than the “Min.” value is applied, the
input voltage is guaranteed as high level voltage.
Low-level input voltage
V
IL
Indicates the voltage, applied to the input pins of the device, which indicates
the low level state for normal operation of the input buffer.
* If a voltage that is equal to or less than the “Max.” value is applied, the
input voltage is guaranteed as low level voltage.
Hysteresis voltage
V
H
Indicates the differential between the positive trigger voltage and the negative
trigger voltage.
Input rise time
t
ri
Indicates allowable input rise time to input signal transition time from
0.1
×
V
DD
to 0.9
×
V
DD
.
Input fall time
t
fi
Indicates allowable input fall time to input signal transition time from
0.9
×
V
DD
to 0.1
×
V
DD
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD720114GA-YEU-ATR | 制造商:Renesas Electronics Corporation 功能描述:I/O CNTRLR USB CNTRLR 48TQFP - Trays |
| UPD720114K9-4E4-A | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 HUB CTRL, 4-PORTS, 40-PIN PLASTIC QFN (6MMX6MM) - Trays |
| UPD720114K9-4E4-SSA-A | 制造商:Renesas Electronics Corporation 功能描述: |
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| UPD720130GC-9EU-A | 制造商:NEC Electronics Corporation 功能描述:BRIDGE USB TO IDE SMD TQFP100 |
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