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參數(shù)資料
| 型號： | UPD7229 |
| 廠商： | NEC Corp. |
| 英文描述： | 1/8, 1/16 DUTY LCD CONTROLLER/DRIVER |
| 中文描述： | 1 / 8，1 / 16稅LCD控制器/驅(qū)動 |
| 文件頁數(shù)： | 15/64頁 |
| 文件大?。?/td> | 314K |
| 代理商： | UPD7229 |
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Data Sheet S10299EJ4V0DS00
15
μ
PD16434
2.5 Data Memory
The data memory is a static RAM configured by two 50-word
×
8-bit banks. It is used for storing display data.
Figure 2–5. Data Memory Configuration
Bank 0
(50 x 8)
Bank 1
(50 x 8)
00H
31H
00H
31H
The data memory bank is specified by the bank flag in the data pointer, and the address in the bank is specified
by the 6-bit binary counter in the data pointer.
The 8-bit data, written to the serial/parallel interface by the CPU, is used for operation or decoded according to
the specified data processing mode, and is written into the data memory.
The data memory contents can be directly manipulated by a bit manipulation instruction.
When the
μ
PD16434 is set in the read mode, the data memory contents are output to the CPU through the
serial/parallel interface.
The data memory contents are read out in bit units in synchronization with the row drive signal and are sent to the
column driver for driving the LCD. This operation is performed independently from command/data write/read operation
with the CPU, which is performed through the serial/parallel interface. Display data read out operation differs,
depending on the number of time-divisions.
(1) 8-time-division (single/multi-chip configuration)
The contents of the display data in bank 0 or bank 1, whichever is specified by the SMM command, are read
out to the column driver.
Figure 2–6 shows bits correspondence for the row driver and column driver for the data memory. If the data
located at the Rn and Cm intersection is 1, the corresponding LCD dot is ON. If the data is 0, the dot is OFF.
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