參數(shù)資料
型號(hào)： UPD72870F1-FA2
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 337K
代理商： UPD72870F1-FA2
Preliminary Data Sheet S13925EJ2V0DS00
15
μ
PD72870,72871
(2/2)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PORTDIS
I
105
H16
Port Disable
SUS_RESM = “1”
This selected state will be loaded to Disabled bit which
allocated PHY register Port Status Page.
1:Disable
At this time, all ports will be disabled (
μ
PD72870: 3ports,
μ
PD72871: 1port).
SUS_RESM=“0”
PORTDIS has no effect.
SUS_RESM
I
106
G15
Suspend/Resume Function Select
1 : Suspend/Resume On (P1394a draft 2.0 compliant)
0 : Suspend/Resume Off (P1394a draft 1.3 compliant)
CPS
I
123
A15
-
-
Cable Power Status Input
Note
Note
Please refer to
4.1.3 CPS
.
1.3 PHY Signals: (9 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
TpBias0
O
128
C14
-
-
Port-1 Twisted Pair Bias Voltage Output
Note 2
TpBias1
Note1
O
127
B14
-
-
Port-2 Twisted Pair Bias Voltage Output
Note 2
TpBias2
Note1
O
126
A14
-
-
Port-3 Twisted Pair Bias Voltage Output
Note 2
RI0
-
121
A16
-
-
Resistor0 for Reference Current Setting
Note 3
RI1
-
122
B16
-
-
Resistor1 for Reference Current Setting
Note 3
FIL1
-
114
E15
-
-
APLL Filter Terminal
(No need to assemble)
FIL0
-
115
E16
-
-
APLL Filter GND
(No need to assemble)
XI
I
117
D15
-
-
X’tal XI
XO
O
118
D16
-
-
X’tal XO
Note 1.
μ
PD72870 only. In
μ
PD72871, it is open.
2.
If unused port, please refer to
4.1.4 Unused Port
.
3.
Please refer to
4.5 RI0, RI1
.
1.4 PHY Control Signals: (5 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PC0-PC2
I
93-95
K15,L15,
L16
-
3.3
Power Class Input
Note 1
CMC
I
96
K16
-
3.3
Configuration Manager Capable
Note 1
P_RESETB
I
110
F16
PHY Power on Reset Input
Note 2
Note 1.
Please refer to
4.3 PC0-PC2, CMC
.
2.
Please refer to
4.4 P_RESETB
.
#
#
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