參數(shù)資料
型號(hào)： UPD72870F1-FA2
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 337K
代理商： UPD72870F1-FA2
Preliminary Data Sheet S13925EJ2V0DS00
24
μ
PD72870,72871
3.1.1 Offset_00 Vendor ID Register
This register identifies the manufacturer of the
μ
PD72870, 72871. The ID is assigned by the PCI_SIG committee.
Bits
R/W
Description
15-0
R
Constant value of 1033H.
3.1.2 Offset_02 DeviceID Register
This register identifies the type of the device for the
μ
PD72870, 72871. The ID is assigned by NEC Corporation.
Bits
R/W
Description
15-0
R
Constant value of 00CDH (
μ
PD72870 ).
Constant value of 00CEH (
μ
PD72871).
3.1.3 Offset_04 Command Register
The register provides control over the device’s ability to generate and respond to PCI cycles.
Bits
R/W
Description
0
R
I/O enable
Constant value of 0. The
μ
PD72870, 72871 does not respond to PCI I/O
accesses.
1
R/W
Memory enable
Default value of 1. It defines if the
μ
PD72870, 72871 responds to PCI
memory accesses. This bit should be set to one upon power-up reset.
0: The
μ
PD72870, 72871 does not respond to PCI memory cycles
1: The
μ
PD72870, 72871 responds to PCI memory cycles
2
R/W
Master enable
Default value of 1. It enables the
μ
PD72870, 72871 as bus-master on the
PCI-bus.
0: The
μ
PD72870, 72871 cannot generate PCI accesses by being a bus-master
1: The
μ
PD72870, 72871 is capable of acting as a bus-master
3
R
Special cycle monitor enable
Constant value of 0. The special cycle monitor is always
disabled.
4
R/W
Memory write and invalidate enable
Default value of 0. It enables Memory Write and Invalid
Command generation.
0: Memory write must be used
1: The
μ
PD72870, 72871, when acts as PCI master, can generate the command
5
R
VGA color palette invalidate enable
Constant value of 0. VGA color palette invalidate is
always disabled.
6
R/W
Parity error response
Default value of 0. It defines if the
μ
PD72870, 72871 responds to PERR.
0: Ignore parity error
1: Respond to parity error
7
R
Stepping enable
Constant value of 0. Stepping is always disabled.
8
R/W
System error enable
Default value of 0. It defines if the
μ
PD72870, 72871 responds to SERR.
0: Disable system error checking
1: Enable system error checking
9
R
Fast back-to-back enable
Constant value of 0. Fast back-to-back transactions are only
allowed to the same agent.
15-10
R
Reserved
Constant value of 000000.
#
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