參數(shù)資料
型號(hào)： UPD72870FA2
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁數(shù)： 37/48頁
文件大?。?/td> 311K
代理商： UPD72870FA2
Preliminary Data Sheet S13925EJ2V0DS00
37
μ
PD72870,72871
(3) W_GUIDHi register (Base address + 0x938)
31
0
W_GUIDHi
Field
Bits
R/W
Default value
Description
W_GUIDHi
31-0
R/W
Undefined
GlobalUniqueIDHi value. The value is loaded into OHCI GlobalUniqueIDHi
register in OHCI register (Offset+024H bit 31-0).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.5.5].
(4) W_GUIDLo register (Base address + 0x93C)
31
0
W_GUIDLo
Field
Bits
R/W
Default value
Description
W_GUIDLo
31-0
R/W
Undefined
GlobalUniqueIDLo value. The value is loaded into GlobalUniqueIDLo register
in OHCI register (Offset+028H bit 31-0).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.5.5].
(5) Parameters Write register (Base address + 0x940)
31
7
6
4
3
1
0
- 0 -
PAGE_S
- 0 -
PAR
_W
Field
Bits
R/W
Default value
Description
-
31-7
-
-
Reserved. Write 0 to these bits.
PAGE_S
6-4
R/W
000
Write register select page. The bit field returns zero when read.
000: Select SUBID register and LATVAL register.
001: Select W_GUIDHi register and W_GUIDLo register.
010: Select W_GENERAL register (W_GENERAL_0 and W_GENERAL_1).
011: Select W_GENERAL register (W_GENERAL_2 and W_GENERAL_3).
100: Select W_PHYS register (W_ programPhyEnable,
W_aPhyEnhanceEnable).
101: Select W_CIS register (W_CIS_EVEN - W_CIS_ODD).
-
3-1
-
-
Reserved. Write 0 to these bits.
PAR_W
0
R/W
0
Write control signal. The bit field returns zeros when read.
1: Write the value of select page defined PAGE_S. One write transaction is
the units of 8 byte.
0: Ignored.
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