參數(shù)資料
型號(hào)： UPD72871
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁(yè)數(shù)： 28/48頁(yè)
文件大?。?/td> 337K
代理商： UPD72871
Preliminary Data Sheet S13925EJ2V0DS00
28
μ
PD72870,72871
3.1.16 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the
μ
PD72870, 72871, the NEC’s
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R/W
Default value of 00H. It specifies which input of the host system interrupt controller the
interrupt pin of the
μ
PD72870, 72871 is connected to.
3.1.17 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the
μ
PD72870, 72871, the NEC’s
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
3.1.18 Offset_3E Min_Grant Register
This register specifies how long of a burst period the
μ
PD72870, 72871 needs, assuming a clock rate of 33MHz.
Resolution is in units of
μ
s. The value should be loaded into the register from the external serial EEPROM upon
power-up reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_3F Max Lat Register
This register specifies how often the
μ
PD72870, 72871 needs to gain access to the PCI-bus, assuming a clock
rate of 33MHz. Resolution is in units of
μ
s. The value should be loaded into the register from the external serial
EEPROM after hardware reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.20 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this
register. It is reserved for OpenHCI use only.
Bits
R/W
Description
0
R/W
PCI global SWAP
Default value of 0. When this bit is 1, all quadrates read from and written to
the PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansion
ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not
required for motherboard implementations.
31-1
R
Reserved
Constant value of all 0.
相關(guān)PDF資料
PDF描述
UPD72870GM-8ED IEEE1394 1-CHIP OHCI HOST CONTROLLER
UPD750104GB-XXX-3BS-MTX MICROCONTROLLER|4-BIT|UPD75XL CPU|CMOS|QFP|44PIN|PLASTIC
UPD750108CUA 4 BIT SINGLE-CHIP MICROCONTROLLER
UPD750104 4 BIT SINGLE-CHIP MICROCONTROLLER
UPD750104A 4 BIT SINGLE-CHIP MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD74HC04C 制造商:Panasonic Industrial Company 功能描述:IC
UPD750068GT-396 制造商:Renesas Electronics Corporation 功能描述:
UPD7507C189 制造商:Panasonic Industrial Company 功能描述:IC
UPD7508CU265 制造商:Panasonic Industrial Company 功能描述:IC
UPD75208 制造商:Panasonic Industrial Company 功能描述:IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*