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參數(shù)資料
| 型號(hào)： | UPD72871FA2 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 1-CHIP OHCI HOST CONTROLLER |
| 中文描述： | IEEE1394連接1 - OHCI主機(jī)控制器芯片 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 311K |
| 代理商： | UPD72871FA2 |
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Preliminary Data Sheet S13925EJ2V0DS00
27
μ
PD72870,72871
3.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,
configuration, and status registers) of the
μ
PD72870, 72871, while the BIOS is expected to set this value during
power-up reset.
Bits
R/W
Description
11-0
R
Constant value of 000H. These bits are “read-only”.
31-12
R/W
-
3.1.12 Offset_20 Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC’s
μ
PD72870, 72871 function. While the ID is
assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial ROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 1033H.
3.1.13 Offset_22 Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC’s
μ
PD72870, 72871 function. While the ID
is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 0063H.
3.1.14 Offset_30 Expansion Rom Base Address Register
This register is not supported by the current implementation of the
μ
PD72870, 72871.
Bits
R/W
Description
31-0
R
Reserved
Constant value of 0.
3.1.15 Offset_34 Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the
μ
PD72870, 72871, the NEC’s
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 60H. The value represents an offset into the
μ
PD72870, 72871’s PCI
Configuration Space for the location of the first item in the New Capabilities Linked List.
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