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參數(shù)資料
| 型號： | UPD72873GC-YEB |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 269K |
| 代理商： | UPD72873GC-YEB |
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Preliminary Data Sheet S15305EJ2V0DS
16
μ
PD72873
2.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0
1
2
3
4
5
6
7
1000
AStat
BStat
Child
Connected
Bias
Disabled
1001
Negotiated_speed
Int_enable
Fault
Reserved
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Table 2-2. Bit Field Description
Field
Size
R/W
Reset value
Description
AStat
2
R
XX
A port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
BStat
2
R
XX
B port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
Child
1
R
Child node status value.
1: Connected to child node
0: Connected to parent node
Connected
1
R
0
Connection status value.
1: Connected
0: Disconnected
Bias
1
R
Bias voltage status value.
1: Bias voltage
0: No bias voltage
Disabled
1
R/W
See
Description
The reset value is set to 0: Enabled.
Negotiated_
Speed
3
R
Shows the maximum data transfer rate of the node connected to this port.
000: 100 Mbps
001: 200 Mbps
010: 400 Mbps
Int_enable
1
R/W
0
When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,
Disabled or Fault bits change state.
Fault
1
R/W
0
Set to 1 if an error occurs during Suspend/Resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Reserved
-
R
000…
Reserved. Read as 0.
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