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參數(shù)資料
| 型號： | UPD72873GC-YEB |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大小： | 269K |
| 代理商： | UPD72873GC-YEB |
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Preliminary Data Sheet S15305EJ2V0DS
25
μ
PD72873
3.1.22 Offset_64 Power Management Control/Status Register
This is a 16-bit register that provides control status information of the
μ
PD72873.
Bits
R/W
Description
1,0
R/W
PowerState
Default value is undefined. This field is used both to determine the current power
state of the
μ
PD72873 and to set the
μ
PD72873 into a new power state.
00: D0 (DMA contexts: ON, Link Layer: ON, PME will be asserted upon INTA being active)
01: D1 (DMA contexts: OFF, Link Layer: ON, PME will be asserted upon INTA being active)
10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in
the
μ
PD72873.
7-2
R
Reserved
Constant value of 000000.
8
R/W
PME_En
Default value of 0. This field is used to enable the specific power management
features of the
μ
PD72873.
12-9
R
Data_Select
Constant value of 0000.
14,13
R
Data_Scale
Constant value of 00.
15
R/W
PME_Status
Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is
ignored.
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