參數(shù)資料
型號(hào)： UPD72874
廠商： NEC Corp.
英文描述： IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
中文描述： IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器
文件頁(yè)數(shù)： 23/40頁(yè)
文件大?。?/td> 297K
代理商： UPD72874
Preliminary Data Sheet S15306EJ2V0DS
23
μ
PD72874
3.1.16 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the
μ
PD72874, the NEC’s implementation of
the 1394 OHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
3.1.17 Offset_3E Min_Gnt Register
This register specifies how long of a burst period the
μ
PD72874 needs, assuming a clock rate of 33 MHz.
Resolution is in units of
μ
s. The value should be loaded into the register from the external serial EEPROM upon
power-up reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.18 Offset_3F Max_Lat Register
This register specifies how often the
μ
PD72874 needs to gain access to the PCI-bus, assuming a clock rate of 33
MHz. Resolution is in units of
μ
s. The value should be loaded into the register from the external serial EEPROM
after hardware reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OHCI specific. Vendor options are not allowed in this
register. It is reserved for OHCI use only.
Bits
R/W
Description
0
R/W
PCI global SWAP
Default value of 0. When this bit is 1, all quadrates read from and written to
the PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansion
ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not
required for motherboard implementations.
31-1
R
Reserved
Constant value of all 0.
3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the
Next_Item_Ptr describes the location of the next item in the
μ
PD72874’s Capability List.
Bits
R/W
Description
7-0
R
Cap_ID
Constant value of 01H. The default value identified the Link List item as being the PCI
Power Management registers, while the ID value is assigned by the PCI SIG.
15-8
R
Next_Item_Ptr
Constant value of 00H. It indicated that there are no more items in the Link
List.
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