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參數(shù)資料
| 型號： | UPD72874 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER |
| 中文描述： | IEEE1394連接的OHCI 1.1標準3PORT物理層鏈路1 -芯片的主機控制器 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 297K |
| 代理商： | UPD72874 |
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Preliminary Data Sheet S15306EJ2V0DS
30
μ
PD72874
4.1.2 Cable Interface Circuit
Each port is configured with two twisted-pairs of TpA and TpB.
TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.
During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is
encoded, converted from parallel to serial and transmitted.
While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel
after synchronization by SCLK
Note
, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate
of 100/200/400 Mbps.
The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of
the 1394 bus is transmitted to the state machine in the LSI.
Note
The SCLK is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the
μ
PD72874.
4.1.3 CPS
Connect an external resistor of 390 k
between the CPS pin and the power cable, and an external resistor of 100
k
between the CPS pin and the GND to monitor the power of the power cable.
If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed.
4.1.4 Unused Ports
TpAp, TpAn : Not connected
TpBp, TpBn : AGND
TpBias : Not connected
4.2 PLL and Crystal Oscillation Circuit
4.2.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
4.2.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
4.3 PC0 to PC2
The PC0 to PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer
to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can
be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up
or pull-down resistor of 1 k
based on the application.
4.4 P_RESET
Connect an external capacitor of 0.1
μ
F between the pins P_RESET and GND. If the voltage drops below 0 V, a
reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
4.5 RI0, RI1
Connect an external resistor of 9.1 k
± 0.5 % to limit the LSI’s current.
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