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參數(shù)資料
| 型號(hào)： | uPD750068GT |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 56/82頁(yè) |
| 文件大小： | 460K |
| 代理商： | UPD750068GT |
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μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
56
Data Sheet U10165EJ2V0DS00
Main System Clock Oscillator Characteristics (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended
Constants
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
resonator
Oscillation frequency
(f
X
)
Note 1
1.0
6.0
Note 2
MHz
Oscillation
stabilization time
Note 3
After V
DD
reaches
oscillation voltage
range MIN. value
4
ms
Crystal
resonator
Oscillation frequency
(f
X
)
Note 1
1.0
6.0
Note 2
MHz
Oscillation
stabilization time
Note 3
V
DD
= 4.5 to 5.5 V
10
ms
30
External
clock
X1 input frequency
(f
X
)
Note 1
1.0
6.0
Note 2
MHz
X1 input high-/
low-level width
(t
XH
, t
XL
)
83.3
500
ns
Notes 1.
The oscillation frequency and X1 input frequency shown above indicate only oscillator characteristics.
Refer to AC Characteristics for instruction execution time.
If the oscillation frequency is 4.19 MHz < f
X
≤
6.0 MHz at 1.8 V
≤
V
DD
< 2.7 V, do not select the processor
clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95
μ
s, falling
short of the rated value of 0.95
μ
s.
The oscillation stabilization time is the time required to stabilize oscillation after V
DD
has been applied
or STOP mode has been released.
2.
3.
Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
X1
X2
X1
X2
C1
C2
X1
X2
C1
C2
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