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參數(shù)資料
| 型號(hào)： | UPD750104 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 37/80頁 |
| 文件大小： | 525K |
| 代理商： | UPD750104 |
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37
μ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Table 9-1. Status of the Hardware after a Reset (1/2)
Program counter (PC)
PSW
Stack pointer (SP)
Stack bank selection register (SBS)
Data memory (RAM)
General-purpose registers (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Timer/event
counter
Timer counter
Clock timer
Serial interface
4 low-order bits at address 0000H
in program memory are set in PC
bits 11 to 8, and the data at address
0001H are set in PC bits 7 to 0.
5 low-order bits at address 0000H
in program memory are set in PC
bits 12 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Held
0
0
Bit 6 at address 0000H in
program memory is set in RBE,
and bit 7 is set in MBE.
Undefined
1000B
Held
Held
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Held
0
0
Held
4 low-order bits at address 0000H
in program memory are set in PC
bits 11 to 8, and the data at address
0001H are set in PC bits 7 to 0.
5 low-order bits at address 0000H
in program memory are set in PC
bits 12 to 8, and the data at address
0001H are set in PC bits 7 to 0.
Undefined
0
0
Bit 6 at address 0000H in program
memory is set in RBE, and bit 7 is
set in MBE.
Undefined
1000B
Undefined
Undefined
0, 0
Undefined
0
0
0
FFH
0
0, 0
0
FFH
0
0, 0
0
Undefined
0
0
Undefined
Generation of a RESET signal
during operation
Generation of a RESET signal in
a standby mode
Hardware
Carry flag (CY)
Skip flags (SK0 to SK2)
Interrupt status flags (IST0, IST1)
Bank enable flags (MBE, RBE)
μ
PD750104
μ
PD750106, 750108
Counter (BT)
Mode register (BTM)
Watchdog timer enable flag
(WDTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT flip-flop
Counter (T1)
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT flip-flop
Mode register (WM)
Shift register (SIO)
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Basic interval
timer/ watchdog
timer
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