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μ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
10
3.2 Non-Port Pins
Notes 1.
The circle (
2.
With a noise eliminator/asynchronously selectable
3.
Asynchronous
) indicates the Schmitt trigger input.
B
B
F
F
M
B
Function
Inputs external event pulse to the timer/event
counter
Timer/event counter output
Timer counter output
Clock output
Arbitrary frequency output (for buzzer output or
system clock trimming)
Serial clock I/O
Serial data output
Serial data bus I/O
Serial data input
Serial data bus I/O
Edge detection vectored interrupt input (both
rising and falling edges are detected)
Rising edge detection testable input
Falling edge detection testable input
Falling edge detection testable input
Pin for connecting a resistor (R) or capacitor (C)
for main system clock oscillation. An external
clock cannot be input.
Crystal connection pin for subsystem clock
generation. When external clock signal is used, it
is applied to XT1, and it reverse phase signal is
applied to XT2.
XT1 can be used as a 1-bit input (test).
System reset input (active low)
Internally connected. (To be connected directly to
V
DD
)
Positive power supply
Ground potential
Input/
output
Input
Output
I/O
Input
Input
Input
Input
Input
-
-
Input
-
Input
-
-
-
When reset
Input
Input
Input
Input
Input
Input
-
-
-
-
-
-
Edge detection vectored interrupt input
(detection edge selectable). A noise eliminator
can be selected when INT0/P10 is used.
Shared
pin
P13
P20
P21
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 - P63
P70 - P73
-
-
-
-
-
-
Note 3
Note 2
Note 3
I/O circuit
type
Note 1
-C
E-B
-A
-B
-C
-C
-A
F
-A
F
-
-
-
-
-
B
Pin name
TI0
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
KR4 - KR7
CL1
CL2
XT1
XT2
RESET
IC
V
DD
V
SS