參數(shù)資料
型號： UPD750106GB-XXX-3BS-MTX
廠商： NEC Corp.
英文描述： MICROCONTROLLER|4-BIT|UPD75XL CPU|CMOS|QFP|44PIN|PLASTIC
中文描述： 單片機| 4位| UPD75XL的CPU |的CMOS | QFP封裝| 44PIN |塑料
文件頁數(shù)： 36/80頁
文件大小： 525K
代理商： UPD750106GB-XXX-3BS-MTX
μ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
36
9. RESET FUNCTION
The
μ
PD750108 is reset with the external reset signal (RESET) or the reset signal received from the basic interval
timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 9-1 shows the
configuration of the reset circuit.
Figure 9-1. Configuration of Reset Functions
When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Figure 9-2 shows the
reset operation timing.
Figure 9-2. Reset Operation by Generation of RESET Signal
Note
56/f
CC
(28
μ
s at 2.0 MHz, 56
μ
s at 1.0 MHz)
WDTM
RESET
Internal reset signal
Reset signal from basic
interval timer/watchdog timer
Internal bus
RESET signal is generated
Operating mode or
standby mode
HALT mode
Operating mode
Internal reset operation
Wait
Note
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