參數(shù)資料
型號: UPD75066GB
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機(jī)
文件頁數(shù): 27/68頁
文件大小: 640K
代理商: UPD75066GB
27
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
6. INTERRUPT FUNCTIONS
The
μ
PD75068 has six different interrupt sources. In addition, multiple interrupts with priority control are
possible. Two types of test sources are provided. Of these test sources, INT2 has two types of edge detection
testable inputs.
Table 6-1. Interruption Source Types
Interruption
Order
Note1
Vectored Interrupt Request Signal
(Vector table address)
Interruption Source
IN/OUT
(Reference time interval signal from
basic interval timer)
(Detection of both rising edge and
falling edge is valid.)
OUT
2
VRQ2 (0004H)
OUT
3
VRQ3 (0006H)
(Serial data transmission completion
signal)
(Coincidence signal of programmable
timer/counter count register and modulo
register)
INTT0
IN
5
VRQ5 (000AH)
(Detection of rising edge of input to
INT2 pin or detection of falling edge of
any input to KR0 to KR3)
INT2
Note2
OUT
INTW
Note2
(Signal from watch timer)
IN
Notes 1.
The interruption order shows the priority order of the pins when several interruption requests occur
at the same time.
2.
Test source. Like the interruption source, it is influenced by the interruption enable flag. However,
vectored interrupt will not occur.
The interrupt control circuit of the
μ
PD75068 has the following functions:
Hardware controlled vectored interrupt function which can control whether or not to acknowledge an
interrupt based on the interrupt flag (IE
×××
) and interrupt master enable flag (IME)
The interrupt start address can be set arbitrarily.
Interrupt request flag (IRQ
×××
) test function (an interrupt generation can be confirmed by software)
Standby mode release (interrupts to be released can be selected by the interrupt enable flag)
IN
INTBT
INT4
(Selection of rising edge detection or
falling edge detection)
INT0
INT1
INTCSI
VRQ1 (0002H)
1
Test input signal (Set IRQ and IRQW)
VRQ4 (0008H)
4
IN
OUT
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