9
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Pin name
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
AN0 - AN3
AN4 - AN7
AV
REF
AV
SS
X1, X2
XT1, XT2
RESET
IC
V
DD
V
SS
I/O circuit
type
Note 1
-C
B
E-B
E-B
E-B
-A
F
-B
F
-C
M
-C
-C
B
-D
Y-A
-D
Z
Z
–
–
–
–
–
Shared
with
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 - P63/
AN4 - AN7
P110 - P113
P60 - P63/
KR0 - KR3
–
–
–
–
–
–
–
–
When reset
–
Input
Input
Input
Input
Input
Input
–
–
–
Input
Input
–
–
–
–
–
–
–
–
Input/
output
Input
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
I/O
Input
I/O
Input
–
Input
Input
Input
–
–
–
Function
Input for receiving external event pulse signal for
timer/event counter
Timer/event counter output
Clock output
Output frequency selectable
(for buzzer output or system clock trimming)
Serial clock I/O
Serial data output
Serial bus I/O
Serial data input
Serial bus I/O
Edge-detective vectored interrupt input
(both rising and falling edges enabled)
Edge-detective vectored interrupt input
(detection edge selectable)
Edge-detective testable input
(rising edge detection)
Parallel falling edge detection testable input
For A/D converter only
Crystal/ceramic connection for main system clock
generation. When external clock signal is used,
the signal should be applied to X1, and its reverse
phase signal to X2.
Crystal connection for subsystem clock genera-
tion. When external clock signal is used, the
signal should be applied to XT1, and its reverse
phase signal to XT2. XT1 can be used as a 1-bit
input (test).
System reset input
Internally connected.
(Connect this pin directly to V
DD
)
Positive power supply
GND potential
3.2 Non-Port Pins
8-bit analog input
Reference voltage input
GND potential
B
B
Note 2
Note 3
Note 3
Notes 1.
The circle (
) indicates the Schmitt trigger input.
2.
Clock synchronous
3.
Asynchronous